发明名称 DUAL-FREQUENCY MATCHING CIRCUIT
摘要 The connection topology of input terminals (2), elements (4a, 4b, 4c and 4d) and load (5) is designed similarly to a "seven-segment display" that is often used to display numerals on a calculator or a digital watch. Specifically, suppose in the three horizontally running segments of the seven-segment display, the top and bottom ones are associated with the input terminals (2) and the load (5) is allocated to the other horizontal one. Then, the other four vertical segments are associated with the elements (4a, 4b, 4c and 4d), which may be an inductor with an inductance of 2.132 nH, an inductor with an inductance of 8.266 nH, an inductor with an inductance of 0.596 nH, and a capacitor with a capacitance of 2.097 pF, respectively. By adopting this circuit configuration, the total number of elements can be reduced to four and the loss can be reduced significantly. Since the resonant circuits can be eliminated and the size of the ladder circuit can be reduced, impedance matching is achieved with a high degree of stability in spite of a variation in the impedance of the load (5).
申请公布号 US2009189710(A1) 申请公布日期 2009.07.30
申请号 US20090352285 申请日期 2009.01.12
申请人 PANASONIC CORPORATION 发明人 SANGAWA USHIO
分类号 H03H7/38 主分类号 H03H7/38
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