| 摘要 |
A disclosed embodiment is a double data rate (DDR) input block comprising first and second input registers corresponding to a DDR input of the DDR input block. The first and second input registers are coupled to the DDR input. The DDR input block is configured to load a first data into the first input register and a second data into the second input register during a single clock cycle of a system clock, thereby operating at double data input during a single clock cycle. In one embodiment a single data rate/double data rate (SDR/DDR) input block may be operated in either SDR or DDR mode. In one embodiment, the DDR input block may be used with a scannable output reduction block. The DDR input block may be used in systems utilizing a content addressable memory (CAM) or a random access memory (RAM), or other types of memory devices.
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