发明名称 RETICLE, LAYOUT METHOD OF WIRE AND VIA, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To enhance via resolution, and to restrain a via shape from being distorted and shortage from occurring between a via and a via, and the like, without worsening a degree of integration of the vias for interwire connection. <P>SOLUTION: This reticle is used for forming the plurality of vias of connecting the first wire 103 and the second wire 105, the first wire 103 and the second wire 105 are orthogonal each other, a plurality of via opening patterns 101 for forming the plurality of vias is formed into a rectangular shape, each side of the via opening patterns 101 is arranged to be diagonal to a wiring direction, and the minimum space d1 between the adjacent two via opening patterns 101 arranged diagonally is larger than the minimum space between the via opening patterns 101 at the time when the via opening patterns 101 are arranged to make each side in parallel or orthogonal to the first direction and the second direction, by rotating the via opening patterns 101 under the condition of the fixed center point. <P>COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009169366(A) 申请公布日期 2009.07.30
申请号 JP20080010509 申请日期 2008.01.21
申请人 NEC ELECTRONICS CORP 发明人 KUNISHIMA HIROYUKI
分类号 G03F1/70;H01L21/027;H01L21/3205;H01L21/768;H01L21/82;H01L23/52;H01L23/522 主分类号 G03F1/70
代理机构 代理人
主权项
地址