WAFER LEVEL STACK PACKAGE AND METHOD OF FABRICATING THE SAME

摘要

A wafer level stack package and a manufacturing method thereof for improving the effectiveness of the wafer level package are provided to prevent the thickness increase of the total package and increase of the electric signal length. A wafer level stack package(100) comprises a bottom semiconductor chip(104), a top semiconductor chip(106), and a connection terminal(110). The bottom semiconductor chip comprises the rerouting extended to bi-edge. The bottom semiconductor chip comprises the penetration hole in the end part of rerouting. The top semiconductor chip is adhered on the top of the bottom semiconductor chip. The top semiconductor chip comprises the ball land in the part corresponding with the penetration hole. The ball land between top semiconductor chip and penetration hole of the bottom semiconductor chip mutually is connected in the connection terminal.