发明名称 |
A SEMICONDUCTOR DEVICE LAYOUT AND CHANNELING IMPLANT PROCESS |
摘要 |
<p>A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction < 100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.</p> |
申请公布号 |
SG153650(A1) |
申请公布日期 |
2009.07.29 |
申请号 |
SG20050085261 |
申请日期 |
2004.07.22 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. |
发明人 |
YISUO LI;XIAOHONG JIANG;BENISTANT FRANCIS |
分类号 |
H01L21/265;H01L21/336;H01L29/04;H01L29/76;H01L29/772;(IPC1-7):H01L29/76;H01L29/94;H01L31/00 |
主分类号 |
H01L21/265 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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