发明名称 Digital PLL circuit
摘要 A frequency comparator compares frequencies of a reference clock and an output clock to output a frequency comparison signal. A frequency variable circuit is composed of a delay circuit, which has a plurality of inverting circuits connected in series, and a first selection circuit. The first selection circuit selects one of odd output signals outputted from odd-numbered inverting circuits, according to the frequency comparison signal to feedback the selected odd output signal to an input of the delay circuit as a feedback signal. A phase comparator compares phases of the reference clock and the output clock to output a phase comparison signal. A second selection circuit selects one of the odd output signals according to the phase comparison signal to output it as the output clock.
申请公布号 US7567101(B2) 申请公布日期 2009.07.28
申请号 US20050216166 申请日期 2005.09.01
申请人 FUJITSU MICROELECTRONICS LIMITED 发明人 YOKOZEKI WATARU
分类号 H03L7/06;H03L7/07;H03L7/081;H03L7/085;H03L7/087;H03L7/099;H03L7/113 主分类号 H03L7/06
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