发明名称 |
Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition |
摘要 |
A method for operating a memory cell and memory array. The method of memory cell operation entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time.
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申请公布号 |
US7567473(B2) |
申请公布日期 |
2009.07.28 |
申请号 |
US20070857332 |
申请日期 |
2007.09.18 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BREITWISCH MATTHEW J.;LAM CHUNG H.;RAJENDRAN BIPIN |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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