| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce an electric charge required for precharge in a NAND type flash memory capable of reading data from a negative threshold cell. <P>SOLUTION: For instance, when the negative threshold cell is read/verified, a source line of the cell (CELSRC) and a P type well PWELL and N type well NWELL are precharged to the positive voltage Vs (e.g. 1V). At this time, a bit line level control signal BLC is made to "CELSRC + Vt (threshold of a bit line level control transistor)" so that the bit lines BL (BLe, BLo) become the same voltage as that of the source line CELSRC. After this procedure, by making the bit line level control signal BLC to "CELSRC + Vt +ΔBL (potential difference between the bit line BL and the source line CELSRC at the reading out)", the level of the bit line BL is set to a voltage at the reading/verifying time. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
