发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which keeps the address allocation of an address decoder of a pair of memory arrays which are identical in the connection of a main bit line of the pair of memory arrays of the nonvolatile memory, and comprises a connection constitution of a first and a second main bit line which does not cause wiring cross connection. <P>SOLUTION: Gates of gate transistors TR1 to TR4 of a first column gate circuit 20-1 are arranged orthogonally-crossing a first and a second main bit line GBL0, GBL1; drains of two gate transistors TR1, TR2 for connecting the first main bit line GBL0 and two bit lines BL0-1, BL1-1 are formed in a common area RD1; drains of the other two gate transistors for connecting the second main bit line GBL1 and the other two bit lines are formed in the other common area DR2; and the layout pitch of the first and the second main bit line GBL0, GBL1 becomes a repeating pitch of the column gate circuit. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2009158574(A) 申请公布日期 2009.07.16
申请号 JP20070332371 申请日期 2007.12.25
申请人 SAMSUNG ELECTRONICS CO LTD 发明人 KURIYAMA MASAO
分类号 H01L27/10;G11C16/06;H01L21/8247;H01L27/115;H01L29/788;H01L29/792 主分类号 H01L27/10
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