| 摘要 |
PROBLEM TO BE SOLVED: To reduce the man-hour in assertion-based verification. SOLUTION: A method for creating an assertion description to be used in verification of a digital circuit in a digital circuit verification tool which performs the verification comprises outputting, based on operation histories of the digital circuit to a plurality of predetermined verification patterns, information capable of specifying a verification pattern corresponding to an operation history with relatively low occurrence frequency, and creating, with respect to the verification pattern corresponding to the operation history with relatively low occurrence frequency, an assertion description for detecting that the digital circuit shows an operation corresponding to the operation history with low occurrence frequency as an error. COPYRIGHT: (C)2009,JPO&INPIT
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