| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a floating point arithmetic device for performing the parallel processing of the addition (A+B) and subtraction (A-B) of two floating points A and B while making it attainable to perform the conventional floating point product sum operation. <P>SOLUTION: The floating point arithmetic device includes not only a conventional floating point product sum arithmetic unit (FMA) but also one floating point adder for performing the parallel execution of addition (A+B) and subtraction (A-B) to two floating points A and B, wherein the arithmetic device further includes a means for determining whether or not the left shift normalization of 2 bits or more is required for either addition (A+B) or subtraction (A-B). The arithmetic device eliminates the normalization logic of either the addition (A+B) or subtraction (A-B) for which the left shift normalization of 2 bits or more is not required. Thus, it is attainable to improve performance two times as large, and to suppress the circuit scale less than two times as small. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
