REDUCTION OF JITTER IN A SEMICONDUCTOR DEVICE BY CONTROLLING PRINTED CIRCUIT BOARD AND PACKAGE SUBSTRATE STACKUP

摘要

A model and method are provided for lowering device jitter by controlling the stackup of PCB planes (1 -24) so as to minimize inductance between a FPGA (105) and PCB voltage planes (1 -24) for critical core voltages within the FPGA (105). Furthermore, a model and method are provided for lowering jitter by controlling the stackup of package substrate planes so as to minimize inductance between a die and substrate voltage planes for critical core voltages within the die.