TIMING SIGNAL GENERATOR PROVIDING SYNCHRONIZED TIMING SIGNALS AT NON-INTEGER CLOCK MULTIPLES ADJUSTABLE BY MORE THAN ONE PERIOD
摘要
<p>A system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period including a plurality of local edge generators receiving the clock signals, each local generator including local programmable means to record an absolute time at which to generate a timing signal in the current or future period and the means to generate that timing signal at a synchronous even sub¬ division of the clock period resolution. A separate time value is maintained allowing generated timing signals to be delayed by more than one period. An output delay circuit generates the timing signal responsive to a future time value and a phase offset. The phase offset can be provided using a clock multiplier and serial parallel converter to simplify hardware realizations.</p>
申请公布号
WO2009088693(A1)
申请公布日期
2009.07.16
申请号
WO2008US87363
申请日期
2008.12.18
申请人
TERADYNE, INC.;JONES, CHRISTOPHER, C.;MCGOLDRICK, MICHAEL, F.