| 摘要 |
PROBLEM TO BE SOLVED: To provide a high level synthesizer for suppressing the increase in a circuit scale, and designing a logic circuit with an effect of reducing power consumption. SOLUTION: The high level synthesizer comprises: a scheduling unit 111 configured to perform data flow analysis and scheduling to generate a data flow graph showing an operation cycle of an operation from the behavioral description; a scheduling result input/output unit 112 configured to extract a point to be allocated to a register from the data flow graph and output register information 103 indicating the point, the scheduling result input/output unit being provided with dynamic analysis data 104 that includes at least one of the number of times that data at the point has been substituted and the number of times that a value stored at the point has changed by a predetermined simulation; an allocating unit 113 configured to consult dynamic analysis data and allocate circuit elements to the behavioral description; and an RTL description generating unit configured to generate the logic circuit based on the allocation of circuit elements by the allocating unit. COPYRIGHT: (C)2009,JPO&INPIT
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