MEMORY APPARATUS AND METHOD USING ERASURE ERROR CORRECTION TO REDUCE POWER CONSUMPTION

摘要

An error correction circuit coupled to a plurality of memory cells in a memory device includes an error correcting code ("ECC") generator and an ECC controller. The ECC generator is coupled to the memory cells and recognizes data bits stored in the memory cells as a plurality of data bit strings in a first direction and as a plurality of data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC generator generates a respective correction code in the first direction for each data bit string in the first direction and also generates a respective correction code in the second direction for each data bit string in the second direction. The ECC controller is coupled to the memory cells and the ECC generator. The ECC controller identifies a data bit string in the first direction having more than one data bit in error based on the respective correction code in the first direction and identifies a data bit string in the second direction having more than one data bit in error based on the respective correction code in the second direction. The ECC controller causes the data bit shared by the identified data bit string in the first direction and the identified data bit string in the second direction to be changed from a respective existing value to a respective new value different than the respective existing value.