| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To generate a clock signal having a desired phase from input multi-phase clock signals with a relatively small circuit scale. <P>SOLUTION: In a device for generating a clock signal having a desired phase from input multi-phase clock signals, an intermediate clock generator (11) generates, by using one of the input multi-phase clock signals as a reference clock signal, multi-phase intermediate clock signals in which one cycle is equal to a plurality of cycles of the reference clock signal. A first phase selector (12) selects one of the multi-phase intermediate clock signals. A second phase selector (13) selects one of the multi-phase clock signals. A latch circuit (14) latches the intermediate clock signal selected by the first phase selector (12) with the clock signal selected by the second phase selector (13). <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
