| 摘要 |
A data processing apparatus and method are provided for testing stability of memory cells in a memory device. A data processing apparatus comprises a memory device having an array of memory cells for storing data values. Test circuitry is employed in a test mode of operation to execute one or more test patterns in order to detect any memory cells which may malfunction in a normal mode of operation due to cell instability following a write operation, as for example may be caused by body region history effect in embodiments where each memory cell comprises at least one transistor having a body region insulated from a substrate. Each test pattern causes a sequence of access requests to be issued to the memory device whose timing is controlled by a test mode clock signal. Dummy read control circuitry is employed in the test mode of operation, and is responsive at least to each write access request to generate an internal clock signal which has an increased frequency with respect to the test mode clock signal. Further, the dummy read control circuitry is responsive to each write access request to perform using the internal clock signal a write operation to at least one memory cell based on a memory address specified by the write access request, followed by a dummy read operation to the same at least one memory cell, the dummy read operation serving to stress the at least one memory cell with respect to cell stability. This approach provides a very reliable, effective and realistic (in terms of test time) mechanism for detecting memory cells which may malfunction in normal use due to cell instability following a write operation.
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