| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce phase jitter of a hybrid control type PLL circuit in a steady state. <P>SOLUTION: A steady state detection circuit CONV_DET determining whether an output S_PH of a phase comparison circuit PHASE_COMP in a hybrid control type PLL circuit frequently changes is provided, determination that a steady state has not been reached is made if the output S_PH of the phase comparison circuit does not change for a while, determination that the steady state has been reached if the output of the phase comparison circuit frequently changes, and based on results of the determination, a control width of controlling an oscillation frequency of a voltage controlled oscillator circuit VCO by a digital control signal S_DG is changed or (and) a frequency of changing an analog control signal S_AG is changed. Thereby, a control width of the oscillation frequency by the digital control signal after reaching the steady state can be reduced without damaging convergence before reaching the steady state. The phase jitter in the steady state therefore can be reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT |
