Nanoscale CMOS transister with an intrinsic bulk

摘要

A modification to the doping profile of the source of nanoscale MOSFETs is disclosed. The source region comprises a top and bottom region of opposite dopant types. In one embodiment of the invention, the top region does not cover the bottom region completely. In another embodiment, the top region covers the bottom region, in which case connection is made to both of the regions via a trench made into the source. For gate dimensions less than 50 nm and down to 10nm, the extra doped region affects the source and drain potential barriers such that a well defined on and off regions are obtained for intrinsic bulk material. Both p and n channel transistors can be obtained.