| 摘要 |
A digital control loop within power switchers and the like includes a sliding error sampler analog-to-digital converter producing an error value for a digital loop iteration. A predictor variably sets the timing for initiating analog-to-digital conversion of the current error value based on the magnitude of a previous error value for a previous loop iteration, plus margins conversion housekeeping and the step size of the next loop iteration. At a timing prior to a filter reading the error value that equals the number of clock cycles set by the predictor, a timing unit triggers the analog-to-digital conversion, reducing loop latency and improving performance.
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