发明名称 Extension of accuracy of a flash ADC by 1-bit through interpolation of comparator outputs
摘要 ADC accuracy is increased by 1 bit by interpolation of comparator outputs in a comparator array, thereby increasing accuracy without significantly increasing power consumption and size. Specifically, an analog-to-digital converter includes a binary converter and a comparator array, which comprises a plurality of comparator blocks, each block having a primary comparator and an interpolating comparator. The interpolating comparator compares an output signal from the primary comparator with a negative output signal from a primary comparator of another block of the plurality of blocks to generate a least significant bit. The binary converter, which is coupled to the array, converts array output to binary code.
申请公布号 US7561092(B2) 申请公布日期 2009.07.14
申请号 US20080019627 申请日期 2008.01.24
申请人 SIGMA DESIGNS, INC. 发明人 TERO JOHN PHILIP
分类号 H03M1/12;H03M1/34 主分类号 H03M1/12
代理机构 代理人
主权项
地址