发明名称 Programming method to reduce word line to word line breakdown for NAND flash
摘要 A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines adjacent to the selected word line and memory cell being programmed in order to reduce voltage differences between the word lines of the memory cell string or array during a programming cycle. This allows the word line to word line voltage differential to be reduced and thus decreases the likelihood of breakdown or punch through of the insulator materials placed between the adjacent word lines.
申请公布号 US7561469(B2) 申请公布日期 2009.07.14
申请号 US20060390747 申请日期 2006.03.28
申请人 MICRON TECHNOLOGY, INC. 发明人 ARITOME SEIICHI
分类号 G11C16/10;G11C7/02;G11C8/08;G11C16/06;G11C16/12 主分类号 G11C16/10
代理机构 代理人
主权项
地址