| 摘要 |
Parallel adder relates to computing and can be used at construction of arithmetical devices for processes of adding and subtraction. According to the invention to parallel adder i-th byte of which includes input logical element AND, and element OR, additionally are included four logical elements AND with inverter NOT at other input, first and second output elements AND, element AND-NOT and first and second elements OR outputs of which are connected to the first and the second inputs of element AND-NOT output of which is connected to the second input of the first and the second output elements AND outputs of which are outputs of positive and negative sums of i-th byte, and first input of respective output elements AND are connected to output of the first and the second elements OR first inputs of which are connected to output of input element AND, and to output of fourth element AND, respectively. First input of the last one is connected to output of input elements OR, and input of inverter NOT of its second input is input of intermediate sum of i-1-th byte and connected to first output of third element AND. Input of inverter NOT of the second input is connected to output of input element OR and is output of intermediate sum of i-th byte. At that output of third element AND is connected to the second input of the first element OR. Second input of second element OR is connected to output of second element AND with inverter NOT at its other input, first input is input of negative second term. Inverter NOT is connected to the first input of first element AND with inverter at other input and is output of first positive adding, input of inverter NOT is input of negative second term. Positive input of second term are first inputs of input elements AND, and OR, second inputs of those are connected to output of first element AND with inverter at its second input. Technical result is in increase of rate of operation of parallel adder. |
