LOW-POWER HIGH-PERFORMANCE MEMORY CIRCUIT AND RELATED METHOD

摘要

PROBLEM TO BE SOLVED: To provide an integrated circuit in which power consumption is reduced and a chip area is reduced. SOLUTION: The integrated circuit includes: a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to the first source/drain of the second PMOS; a third bias voltage node coupled to the gate of the first PMOS transistor; a fourth bias voltage node coupled to the gate of the first PMOS transistor; a pull-up node coupling the second source/drain of the first NMOS transistor to the first source/drain of the first PMOS transistor; a pull-down node coupling the second source/drain of the second PMOS transistor to the first source/drain of the second NMOS transistor; an input node; a storage node coupling the second source/drain of the first PMOS transistor to the second source/drain of the second NMOS transistor; and an output node. COPYRIGHT: (C)2009,JPO&INPIT