发明名称 CIRCUIT EXTRACTING DEVICE AND METHOD
摘要 PROBLEM TO BE SOLVED: To provide a circuit extracting device easily discriminating a node of interest as a probe point of simulation in an extracted circuit diagram, in extracting the circuit diagram including a parasitic element from layout data. SOLUTION: This circuit extracting device 10 includes a pseudo pattern setting portion 11, a pseudo element setting portion 12, a parasitic element extracting portion 13 and an output portion 14. The pseudo pattern setting portion 11 receives the layout data, and sets one or more pseudo patterns. The pseudo element setting portion 12 inputs the circuit diagram to the layout data, and sets the pseudo elements respectively corresponding to the pseudo patterns. The parasitic element extracting portion 13 extracts the parasitic elements on the basis of the layout data in which the pseudo pattern is set. The output portion 14 combines the parasitic element to the circuit diagram in which the pseudo element is set. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009151620(A) 申请公布日期 2009.07.09
申请号 JP20070329943 申请日期 2007.12.21
申请人 ELPIDA MEMORY INC 发明人 YOSHIKUNI HITOSHI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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