发明名称 |
METHOD AND APPARATUS FOR UNIVERSAL PROGRAM CONTROLLED BUS ARCHITECTURE |
摘要 |
An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.
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申请公布号 |
US2009174431(A1) |
申请公布日期 |
2009.07.09 |
申请号 |
US20090401055 |
申请日期 |
2009.03.10 |
申请人 |
PANI PETER M;TING BENJAMIN S |
发明人 |
PANI PETER M.;TING BENJAMIN S. |
分类号 |
G06F13/36;H03K19/177;H03K19/173 |
主分类号 |
G06F13/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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