| 摘要 |
<p>A reduction in circuit scale and a reduction in power consumption are achieved. On the basis of a test pattern, a semiconductor test apparatus applies a waveform, corresponding to an output of a flip-flop whose state transition timing is controlled, to a device to be tested, thus testing the device. The apparatus includes a clock resolution skew adjust unit that receives a SET signal for changing the flip-flop to a set mode and a RESET signal for changing the flip-flop to a reset mode such that the unit is common to delay data for set and delay data for reset. Since a memory and a latch circuit in the clock resolution skew adjust unit are shared, a reduction in circuit scale and a reduction in power consumption can be achieved.</p> |
