发明名称 LAYOUT DESIGN DEVICE AND LAYOUT DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a layout design device and a layout design method, capable of solving sparseness or denseness of metal of each layer and improving the accuracy of delay calculation by surely preventing delay fluctuation by crosstalk. SOLUTION: The layout design device includes a calculation processing portion 1 that calculates a degree of wire congestion 402 of each layer based on pre-wiring design data 401 to form a desired wiring structure in each layer; a selection processing portion 2 that selects a layer having a power supply which is a lower layer of (n-1)th layer 7 or an upper layer of (n+1)th layer 8 when the degree of wire congestion 402 in a selection area of n-th layer 6 is lower than that of the (n-1)th layer 7 and the (n+1)th layer 8; and an adding processing portion 3 that generates post-addition design data by adding design data which connects the power supply to the (n-1)th layer 7 or the (n+1)th layer 8 to the pre-wiring design data 401. A wiring process and a metal generating process are performed based on the post-addition design data. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009151433(A) 申请公布日期 2009.07.09
申请号 JP20070327136 申请日期 2007.12.19
申请人 NEC ELECTRONICS CORP 发明人 WARIGAI TADASHI
分类号 G06F17/50;H01L21/82 主分类号 G06F17/50
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