PROCESSING PIPELINE HAVING STAGE-SPECIFIC THREAD SELECTION AND METHOD THEREOF

摘要

One or more processor cores (102, 104, 106, 108) of a multiple-core processing device (100) each can utilize a processing pipeline (800) having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fetch, decode and dispatch resources. Further, one or more of the processor cores (102, 104, 106, 108) each can implement dispatch resources configured to dispatch multiple instructions in parallel to multiple corresponding execution units via separate dispatch buses. The dispatch resources further can opportunistically decode and dispatch instruction operations from multiple threads in parallel so as to increase the dispatch bandwidth. Moreover, some or all of the stages (802, 804, 806) of the processing pipelines (800) of one or more of the processor cores (102, 104, 106, 108) can be configured to implement independent thread selection for the corresponding stage.