发明名称 Compander architecture and methods
摘要 Compander architecture and method for ensuring that the components of an output signal are synchronized includes calculating a gain calculation for an input signal, detecting a predetermined condition such as a zero crossing or absence of a zero crossing within a specified period, and ensuring that the result of the gain calculation is providing to the system synchronously with the input signal. The input signal may be divided into one or more signals for processing, and the gain calculation may include one or more power estimations and one or more gain cells associated with the multiple signals, and may further include variable attack and release.
申请公布号 US7558391(B2) 申请公布日期 2009.07.07
申请号 US20000726983 申请日期 2000.11.29
申请人 BIZJAK KARL L 发明人 BIZJAK KARL L.
分类号 H03G7/00;G10L21/02;H03G3/30;H03G3/32;H03G7/06;H03G9/02;H04R3/00;H04R25/00;H04R27/00 主分类号 H03G7/00
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