摘要 |
A digital phase locked loop (DPLL) comprising a digitally implemented voltage controlled oscillator (VCO) for producing a VCO feedback signal, a phase error counter which includes a digital phase-frequency detector for producing a first phase error signal, a quadrature phase detector for producing a second phase error signal and an adder for adding the first and second phase error signals to obtain a combined phase error signal, and two programmable dividers used to cooperatively determine the VCO feedback signal and to provide a DPLL output line sync value synchronized with an input signal.
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