发明名称 STACKED WAFER LEVEL PACKAGE
摘要 <p>A stacked wafer level package is provided to reduce the volume, thickness and weight of a package by using a lower semiconductor chip as a semiconductor chip supporting substrate. A first semiconductor chip(110) has a first bonding pad. A second semiconductor chip(120) is arranged with the first semiconductor chip side by side. A second bonding pad of the second semiconductor chip is arranged in the same direction of the first bonding pad. A third semiconductor chip(130) is arranged on the first semiconductor chip and the second semiconductor chip. A third bonding pad of the third semiconductor chip is exposed between the first semiconductor chip and the second semiconductor chip. A wire structure(150) is electrically connected to the first bonding pad, the second bonding pad and the third bonding pad.</p>
申请公布号 KR20090074508(A) 申请公布日期 2009.07.07
申请号 KR20080000317 申请日期 2008.01.02
申请人 HYNIX SEMICONDUCTOR INC. 发明人 KIM, JONG HOON;SUH, MIN SUK;YANG, SEUNG TAEK;LEE, SEUNG HYUN;KANG, TAE MIN
分类号 H01L23/12 主分类号 H01L23/12
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