| 摘要 |
There exists a speed/power tradeoff in many digital logic circuits. In one embodiment, the tradeoff is used to reduce or minimize power dissipation by slowing down digital logic paths as system performance requirements allow. Relatively low power dissipation occurs when the histogram of logic path delays is packed towards the critical path delay, and the critical path delay is relatively close to the system clock period. In one embodiment, power is reduced by arranging path delays to be relatively slow. In one embodiment, the histogram of path delays is shaped by establishing classes of paths based on path delay, and individually controlling the classes to slow each class down, preferably relatively close to the delay of the critical path.
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