| 摘要 |
In a display device and a control circuit thereof, mounting of a high-capacity memory device for synchronizing the reception cycle of a digital image signal with a drive cycle of the display device or for translating a format of a received digital image signal into a format to be displayed by the display device is avoided, while transmission volume of digital image signals to the display device is reduced to achieve downsizing and power saving. In a display device having a plurality of memory circuits in a pixel, a digital image signal is written into a memory circuit in the pixel using a decoder, whereby digital image data that is received without the use of a high-capacity memory device can be displayed even when the digital image signal is received in an arbitrary cycle. Further, by providing an image processing register in a control circuit of the display device and dividing the pixels of the display device into a plurality of pixel sections, image processing can be performed per pixel section, which leads to reduction in transmission volume of images.
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