| 摘要 |
A delay-locked loop for timing control, includes a voltage-controlled delay line that delays a reference clock to generate a multi-phase clock comprising a plurality of delayed phase clocks; and an up/down controller that receives one of the delayed phase clocks as a feedback clock and generates a frequency up/down control signal based on whether a rising edge of the feedback clock coincides with a falling edge of the reference clock. The delay-locked loop further includes a charge pump that charges or discharges a loop filter connected to the voltage-controlled delay line according to a frequency up/down control signal from the up/down controller; and a harmonic lock detector that compares phases of multiple ones of the delayed phase clocks with a phase of the reference clock, and operates such that the multi-phase clock is locked within a first cycle of the reference clock.
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