TIME-INTERLEAVED SIGMA-DELTA MODULATOR USING SINGLE AMPLIFIER ARCHITECTURE
摘要
A time-interleaved sigma-delta modulator using a single amplifier architecture is provided to implement the modulator with a high dynamic range by increasing an effective sampling frequency. A combiner(210) amplifies and adds a signal inputted from the outside, a fed back signal after quantization, and the fed back signal without the quantization. One or more integrating units delays the signal outputted from the combiner as much as the predetermined clock and multiplies the delayed signal by a constant coefficient. The integrating unit adds the inputted value to the signal and provides the added signal as the fed back signal without quantization to the combiner. A quantizer(220) quantizes the signal outputted from the combiner. A clock delay unit(225) delays the signal outputted from the quantizer and provides the delayed signal as the fed back signal after quantization.
申请公布号
KR20090072053(A)
申请公布日期
2009.07.02
申请号
KR20070140028
申请日期
2007.12.28
申请人
INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
发明人
CHAE, YOUNG CHEOL;LEE, IN HEE;KWON, MIN HO;HAN, GUN HEE