发明名称 REDUCING GATE CD BIAS IN CMOS PROCESSING
摘要 A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.
申请公布号 US2009166629(A1) 申请公布日期 2009.07.02
申请号 US20080241798 申请日期 2008.09.30
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 MEHRAD FREIDOON;CHOI JINHAN;JOHNSON FRANK SCOTT
分类号 H01L21/8238;H01L27/092 主分类号 H01L21/8238
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