| 摘要 |
Embodiments relate to a quarter cycle delay clock generator. According to embodiments, a quarter cycle delay clock generator may include a reference clock generator to generate a reference clock signal, a first logic circuit to catch a first input signal input thereto at a rising edge of the reference clock signal and outputting a first input signal as a first output signal until a next rising edge of the reference clock signal, and a second logic circuit to catch a second input signal input thereto and outputting the second input signal as a second output signal. The first output signal may be inverted and input to the first logic circuit as the first input signal, and the second logic circuit may receive the first output signal from the first logic circuit as the second input signal.
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