发明名称 METHOD FOR EVALUATING GATE OXIDE INTEGRITY IN A SEMICONDUCTOR WAFER AND STRUCTURE FOR THE SAME
摘要 A method for measuring GOI(Gate Oxide Integrity) and a GOI measuring structure for the same are provided to resolve a problem that a defect part is blocked by a polycrystalline silicon by preventing a phenomenon that a part of the polycrystalline silicon is melted into a wafer direction by thermal energy. A reverse bias is applied to a polycrystalline silicon electrode about a silicon wafer(100). A defect is detected by measuring a breakdown voltage when dielectric breakdown of a gate oxide film(101) is generated. The silicon wafer is a P-type wafer. A positive measuring voltage is applied to the polycrystalline silicon electrode(102) about the silicon wafer. The measuring voltage is increased by 200V. A temperature range for measuring the dielectric breakdown is set as 80~200°C.
申请公布号 KR20090071994(A) 申请公布日期 2009.07.02
申请号 KR20070139953 申请日期 2007.12.28
申请人 SILTRON INC. 发明人 KIM, JA YOUNG
分类号 H01L21/66 主分类号 H01L21/66
代理机构 代理人
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