发明名称 POWER PERFORMANCE OPTIMIZATION COMPILER USING SUBSTRATE BIAS CONTROL AND PROCESSOR SYSTEM
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a multiprocessor, capable of efficiently assigning a plurality of parallelizable tasks to processor units (PU), and enhancing the execution efficiency of the whole system in view of performance and power by executing a task which affects the total execution time at high speed and executing a task which does not affect the total execution time at low speed from the viewpoint of power efficiency. <P>SOLUTION: The compiler which divides an input program into a plurality of tasks MT0-MT3 and assigns the tasks to a plurality of PUs (PU0 and PU1) comprises a process for performing the task assignment so as to minimize the total execution time; a power control process for temporarily improving the frequency of a processor executing a task which affects the entire performance; and a power control process for temporarily reducing the frequency of a processor executing a task which does not affect the entire performance. Consequently, processing can be efficiently performed with low power while utilizing the performance of a multiprocessor system to the maximum. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2009146243(A) 申请公布日期 2009.07.02
申请号 JP20070324170 申请日期 2007.12.17
申请人 HITACHI LTD 发明人 KANO HIROAKI
分类号 G06F9/45;G06F1/04;G06F9/30;H01L27/00 主分类号 G06F9/45
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