CLOCK SYNCHRONIZATION CIRCUIT AND OPERATION METHOD THEREOF

摘要

A clock synchronization circuit and a driving method thereof are provided to minimize power consumption and jitter peaking by using an injection locking mode. A phase-locked loop(330) generates a feedback clock signal(CLK-FED) corresponding to an oscillation control voltage(V-CTR). The phase-locked loop generates the oscillation control voltage corresponding to a phase/frequency difference between a reference clock signal(CLK-REF,/CLK-REF) and the feedback clock signal. An injection locking oscillation unit(310) includes a filtering part and an injection locking voltage control oscillation part. The filtering part filters the oscillation control voltage, and outputs the filtered control voltage. The injection locking voltage control oscillation part generates an internal clock signal(CLK-PLL,/CLK-PLL) of a frequency corresponding to the reference clock signal.