| 摘要 |
<p>A delay locked loop comprises a delay line having a plurality of sequentially connected delay elements (E1 to E16). The delay line has an input for receiving an input signal and an output for outputting an output signal. A phase detector (6) is configured to detect a phase difference between the input signal and the output signal, and to generate a control signal based on said difference for supply to at least a part of the delay line. At least one further delay element (EO, E17). One of said at least one further delay element may be further configured to receive said control signal. A clock multiplier (4) can include such a delay locked loop.</p> |
