CLOCK SIGNAL GENERATING CIRCUIT

摘要

A clock signal generator is provided to secure a charging characteristic of a clock signal even though the voltage of an input clock signal is low or the characteristic of the device is bad by bootstrapping a clock signal through a bootstrapping circuit. A first latch control unit(11A) controls the latch operation of an input signal using a clock signal of the contrary phase. A first latch latches the input signal by receiving the control of the first latch control unit. A second latch control unit(11B) controls the latch operation of the signal outputted from the first latch using a clock signal. The second latch is controlled by the second latch control unit and latches the signal outputted from the first latch. The first bootstrap unit(13A) bootstraps the clock signal to a positive direction and a negative direction by using a first condenser and a second condenser. A second bootstrapping unit(13B) bootstraps the clock signal to a positive direction and a negative direction using a third condenser and a fourth condenser.