| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a NAND type flash memory in which a test time can be shortened by reducing largely a time for inputting data for test. <P>SOLUTION: A test control circuit 10 has a first switching circuit 11, a test latch circuit 12, a second switching circuit 13, and a test control signal generating circuit 14. The test latch circuit 12 holds temporarily a data pattern for test inputted through a data input/output buffer 9. By this invention, when the same data pattern for test is latched to a different data latch circuit 4, since a latch is performed by only transfer to the data latch circuit 4 from the test latch circuit 12 without inputting data from the outside whenever, a time required for latching the data pattern for test to the data latch circuit 4 can be shortened largely, and a test time also can be shortened. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
