| 摘要 |
A semiconductor memory device is provided to secure a regular operation margin regardless of a change of an operating environment including a voltage level, temperature, and process in using a system clock of high frequency. A strobe generating part(560) receives an internal strobe signal(PRE-DQS) corresponding to a read command, and drives a plurality of data and an arranged data strobe signal(DQS). A sub driving part(580) receives the internal strobe signal, and outputs a data strobe signal corresponding to a first output data among a plurality of data without delay. The sub driving part includes a first transmission gate, a delay part, and a second transmission gate. The first transmission gate outputs the internal strobe signal as a sub strobe signal during an activation section of a control pulse(QSENPRE-1CLK). The delay part delays the internal strobe signal as a driving time of the strobe generating part. The second transmission gate outputs an output of the delay part as a sub strobe signal during an inactivation section of the control pulse.
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