| 摘要 |
A CMOS transistor and a fabrication method thereof are provided to prevent a short channel effect since channel length is secured in advance by adjusting the channel length as much as trench depth. A well separation film is formed to separate each well(105) after an N-well and a P-well is formed inside semiconductor(103). A first p-type LDD(Lightly Doped Drain) region(113) and a first p+ type source/drain junction layer(117) are formed under the N-well. A first n-type lightly doped drain domain(115) and a first n+ type source / drain contact layer(119) are formed under the P-well. The gate electrode is formed a place where the well separation film is removed, and metal wirings(131,133) connecting with the first p+ type the source / drain contact layer or the first n+ type source / drain contact layer are formed from the n-well and the p-well to the surface.
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