| 摘要 |
A semiconductor memory device is provided to improve read accuracy and to reduce a failure rate by increasing a data retention margin. A memory cell array(1) includes a plurality of bit lines, a plurality of word lines, and a common source line. A bit line control circuit(2) and a word line control circuit(6) are connected to the memory cell array. The bit line control circuit reads data of a memory cell inside the memory cell array through a bit line. A column decoder(3) and a data input/output buffer(4) are connected to the bit line control circuit. A data input/output terminal(5) is connected to a controller(11). The controller has an ECC(Error-Correcting Code) circuit(11-1). The ECC circuit corrects a data read failure of the memory cell. The word line control circuit reads a word line inside the memory cell array. A control signal/control voltage generating circuit(7) controls the memory cell array, the bit line control circuit, the column decoder, the data input/output buffer, and the word line control circuit.
|
