| 摘要 |
A data output circuit of a semiconductor memory device is provided to reduce an amount of a peak current generated in a data output operation by dispersing output timing of a data output strobe clock and an output data. A timing control signal generating unit(10) generates a first timing control signal and a second timing control signal. A first data driving unit(21) generates a first driving data from a first global line data and an internal clock in response to the first timing control signal. A first buffering unit(31) buffers the first driving data, and generates a first output data. A second data driving unit(22) generates a second driving data from a second global line data and an internal clock in response to the second timing control signal. A second buffering unit(32) buffers the second driving data, and generates a second output data.
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