| 摘要 |
An encoder of a multiplier is provided to minimize an area by using a minimum number of transistors without an inverter. A multiplier multiplies multiplier data of plural bits by multiplicand data of plural bits. An encoder of a multiplier includes a plurality of encoding cells. Each encoding cell outputs a plurality of operators by encoding data of two adjacent bits among multiplier data of plural bits. The encoding cell includes an XOR unit, an AND unit and an inverted AND unit and a multiplexer. The XOR unit outputs the first operator by XOR-operating the first multiplier data with the second multiplier data.
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