发明名称 |
Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch |
摘要 |
A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.
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申请公布号 |
US7554839(B2) |
申请公布日期 |
2009.06.30 |
申请号 |
US20060541370 |
申请日期 |
2006.09.30 |
申请人 |
ALPHA & OMEGA SEMICONDUCTOR, LTD. |
发明人 |
BOBDE MADHUR |
分类号 |
G11C11/34;G11C5/06;G11C7/10;H03L5/00 |
主分类号 |
G11C11/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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